1. Technical Field
The present disclosure generally relates to random access memories of SRAM type (Static Random Access Memory) in an integrated circuit.
The disclosure further relates to such memories, be they self-contained or embedded in an electronic circuit comprising other functions such as, for example, a microcontroller.
2. Discussion of the Related Art
Generally, an SRAM cell is based on the use of bistable circuits in CMOS technology. Several cells are arranged in an array by being connected to bit lines and word lines.
Most of the time, the cells comprise six transistors. The bistable circuit is generally comprised of four transistors, and two access transistors connect this bistable circuit to the bit lines while being controlled by a word line.
More recently, it has been attempted to lower the power supply voltage by providing a cell operating under a lower power supply voltage than the levels commonly used for the technology in which the cells are manufactured.
An example of such a cell is described in article “A 32 kb 10 T Sub-threshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS”, by Roy K. et al., published in Solid-State Circuits Conference, Digest of Technical Papers. IEEE International, pp. 388-622, Feb. 3-7, 2008. This cell comprises ten transistors and a stage for switching between the bistable circuit and each transistor of access to the bit line, each of the switching stages comprising a first additional access transistor between the bistable circuit and each access transistor, and a second additional transistor between the access transistor and a potential variable according to the read or write operation. The additional access transistor is controlled by an additional signal. The variable potential is provided by a circuit in a transistor technology which results in limiting the cell operation to the sole low voltages.
A disadvantage of the different known SRAMs is that the content of the bistable circuit is altered in read mode.
Document US-A-2010/0142258 describes another SRAM cell with ten transistors.
FIG. 1 shows a cell with ten transistors such as shown in FIG. 3 of this document. A bistable circuit is based on the principle of two cross-coupled inverters. A first inverter is formed of two transistors in series 2 (M2) and 1 (M1) between potentials VDD and VSS. A second inverter is formed of two transistors in series 3 (M3) and 4 (M4) between potentials VDD and VSS. The control gates of transistors 1 and 2 are connected to the interconnection (node V2) of transistors 3 and 4. The control gates of transistors 3 and 4 are connected to the interconnection (node V1) of transistors 1 and 2. Nodes V1 and V2 are connected to bit lines BL and BLB by series connections of two transistors, respectively 5 (M5) and 8 (ML2), and 6 and 10 (MR2). The contacts common to transistors 5 and 8 are connected to a line GNDX by a transistor 7 (ML1). The contacts common to transistors 6 and 10 are connected to line GNDX by a transistor 9 (MR1). Line GNDX is grounded by a transistor MSLEEP. The gates of transistors 5 and 6 are connected to a word write line WWL and the gates of transistors 8 and 10 are connected to a word read line RWWL. The bodies of transistors 5, 6, 8, and 10 are directly grounded. Once arranged in an array, bit lines BL and BLB are in the vertical direction and lines WWL and RWWL are in the horizontal direction.
At the cell level, this structure seems to solve the issue of the prior cell. However, in an array architecture, unaddressed cells are disturbed when the word read line and the word write line are activated at the same time, which limits multiplexing possibilities. This limitation will be developed hereafter. Further, it would be desirable to improve the low power supply voltage operation.